1. Field of Invention
This invention relates to a method of making a self-aligned silicide (salicide). More particularly, the present invention relates to a method of making a salicide layer that can counteract unwanted junction current leakages.
2. Description of Related Art
As a MOS component's level of integration is increased, resistance in the source/drain terminals of the MOS component will gradually increase to a level comparable to the channel resistance of the MOS component. To ensure integrity between the metal and the shallow junction of the MOS component, and to lower the sheet resistance in the source/drain terminals, self-aligned silicide is currently used in the manufacturing of semiconductor components whenever a line width is less than about 0.5 .mu.m.
FIGS. 1A through 1E show the manufacturing progression of a self-aligned silicide layer according to a conventional method. Referring to FIG. 1A, a substrate 10 is provided. At least one MOS component region 11 is provided over substrate 10. MOS component region 11 includes a gate region 12, lightly doped drain (LDD) regions 12a, and isolating regions 13. The isolating regions 13 can be a shallow trench isolation (STI) region formed using a field oxide layer, for example, as shown in the illustration.
An insulating layer 14, for example, a silicon dioxide layer or a silicon nitride layer, is formed over the substrate 10. Then, an overetching process is performed, in which the insulating layer 14 is overetched to form spacers 15 on the two sidewalls of the gate region 12. The spacers 15 have a height slightly below an upper level of the gate region 12. During the overetching process, an upper layer of the isolating regions 13 will also be removed. Thereafter, using the spacers 15 and gate region 12 as masks, the substrate 10 is doped to form source/drain regions 16, thus forming the structure shown in FIG. 1B.
Subsequently, and referring to FIG. 1C, a metallic layer 17, for example, a titanium layer, is formed over the aforementioned structure. Next, rapid thermal processing (RTP) is performed, during which the metallic layer 17 reacts with a polysilicon at the top surfaces of the gate region 12 and the source/drain regions 16. This reaction forms a metal silicide layer 18 which extends to the isolating regions 13 adjacent to the source/drain regions 16. Thereafter, wet etching is used to remove any unreacted portion of metallic layer 17, thus forming a cross-sectional structure as shown in FIG. 1D.
Referring to FIG. 1E, a dielectric layer 19, for example, a silicon dioxide layer, is formed over the aforementioned structure. Then, the dielectric layer 19 is patterned to form a contact window 20. Contact window 20 exposes the metal silicide layer 18 located on top of the source/drain region 16. Additionally, contact window 20 exposes a portion of the isolating region 13. This completes the manufacturing of the self-aligned silicide layer using the conventional method.
In order to reduce the line width of the metal silicide layers, while maintaining an effective line width over the source/drain regions and gate region, the aforementioned conventional method requires overetching of the spacers. However, the overetching process also etches away part of an upper silicon dioxide layer of the isolating regions 13. Moreover, locating the metal silicide layer 18 at the corner of the isolating region 13, and so near to the junction of the source/drain regions 16, will generate undesired current leakages. As a result, component malfunctions will occur. This problem is especially serious with submicron components having a shallow junction.